1. Field of the Invention
This disclosure relates to a method of adjusting a link speed of a bridge and, more particularly, to a method for automatically adjusting a link speed of a bridge before executing a bus enumeration procedure and a computer system using the same.
2. Description of the Related Art
A built-in peripheral component interconnect express (PCI Express) bridge of a chipset on a motherboard is usually used for connecting an add on card. At present, communication and physical connection between a controller on the add on card and the chipset depend on hardware logic circuits in the chipset.
Generally, a bridge is searched by reading its register. For the PCIe bridge, it provides three registers to indicate buses connected thereto. The three registers are used for storing a primary bus number, a secondary bus number, and a subordinate bus number, respectively. The buses connected with the PCIe bridge can be found via the three numbers. The primary bus number indicates the number of the upstream bus immediately connected with the PCIe bridge. The secondary bus number indicates the number of the downstream bus immediately connected with the PCIe bridge. The subordinate bus number indicates the maximum number among all the downstream bus numbers of the PCIe bridge.
FIG. 1A is a schematic diagram showing a PCIe structure. FIG. 1B is a schematic diagram showing bus numbers. Please refer to FIG. 1A and FIG. 1B. A primary bridge 100 is connected with a PCIe bridge 111 via a bus 0, and the PCIe bridge 111 is connected with a PCIe bridge 121 and a PCIe bridge 131 via a bus 1. The PCIe bridge 121 and the PCIe bridge 131 are connected with a PCIe device 140 and a PCIe device 150 via a bus 2 and a bus 3, respectively.
The primary bus number of the PCIe bridge 111 is 0. Since the secondary bus number is the number of the downstream bus immediately connected thereto, here the secondary bus number is 1. The subordinate bus number is 3. Similarly, for the PCIe bridge 121, the primary bus number is 1. The secondary bus number is the number of the downstream bus immediately connected thereto and therefore it is 2. The subordinate bus number is 2. For the PCIe bridge 131, the primary bus number is 1. The secondary bus number is the number of the downstream bus immediately connected thereto and therefore it is 3. The subordinate bus number is 3. Accordingly, the bus information of the corresponding PCIe bridge can be obtained via reading the aforementioned bus numbers. Further, whether the bridge is connected with a certain peripheral device can be determined via the bus information.
At present, the implementation of a PCI Express interface includes different versions such as PCI Express 1.0, PCI Express 2.0, PCI Express 3.0 and so on. These versions define different speed and related communication protocols, respectively, and therefore incompatibility of the link speed may occur due to different versions when a connection is established between the PCI Express bridge and the controller on the add on card. If a valid connection between the add on card and the PCI Express bridge of the chipset fails to be established, the system may fail to recognize and use the add on card and a peripheral controller on the motherboard, and more seriously, the system may be unstable.
Conventionally, a basic input/output system (BIOS) for initialization provides two connecting modes. One is directly using hardware in the chipset for connection. However, if the connection fails, only a message indicating a connection error occurs is provided. The add on card work normally fails to be determined until an operating system is loaded. If the add on card fails to work normally, the system has to be rebooted and the link speed has to be forcedly adjusted down via options of the BIOS. The other is forcedly adjusting the link speed to the slowest speed. However, it is also inconvenient.